The present invention relates to a ferroelectric random access memory (FRAM) and to a method of fabricating the same, and more particularly the present invention relates to a capacitor structure of the FRAM device and to its method of fabrication.
A ferroelectric random access memory (FRAM) employs a ferroelectric material that has a spontaneous polarization phenomenon. The ferroelectric material has a characteristic in which a polarization (remnant polarization), of the material will remain after removing an external electric field. Additionally, the direction of the polarization can be changed by changing a direction of the external electric field. Exemplary known ferroelectric material include PZT (Pb(Zr,Ti)O3) and SBT (SrBi2Ta2O9).
FRAMs can be classified into separate categories in accordance with their structural elements. One of them uses a transistor that has a ferroelectric for its gate insulation layer. The other comprises unit cells, each of which has an access transistor and a capacitor having a ferroelectric dielectric.
The former type of FRAM has two problems. The first problem is that in the process of fabricating the type of FRAM, oxygen atoms in the ferroelectric film of the ferroelectric film might react with silicon of the substitute to form a silicon oxide layer between the substrate (over the transistor""s channel region) and the ferroelectric film of the gate insulation layer. The second problem concerns a difficulty in forming a high-quality ferroelectric film, which is affected by differences between the lattice constant or thermal expansion coefficient of the silicon substrate relative to the ferroelectric film.
The latter FRAM type may be viewed simplistically as having the same structure as a DRAM cell with the exception of using a ferroelectric film for the dielectric layer of the cell capacitor.
FRAMs have fast read/write operation in comparison with other nonvolatile memory such as EPROM or EEPROM. Additionally, they can carry read/write operations with a single power supply voltage like a DRAM. Thus, the FRAM can have a simple structure that may be related to a peripheral circuit.
The FRAM has another difference from the DRAM, it uses the residual polarization condition of a ferroelectric film for its storage mechanism in contrast to stored charge across the capacitor plates. Therefore, the FRAM doesn""t need to perform refresh operations to restore charge as do the DRAMS. Because of these differences, the FRAM may consume less power and offer improved response time.
For a conventional DRAM, a bottom storage electrode is formed with various features in order to enhance the capacitor""s capacitance. Unlike the capacitors of DRAM devices, the capacitors of FRAMs typically use flat-plate electrodes 36 and 32 as shown in FIG. 4. Flat plates have been used for FRAMs because the capacitance is easy to secure since the ferroelectric film 34 is used even though the cell capacitor is not three-dimensionally formed. Additionally, the flat-plate structure is more easily formed given the material characteristic of the ferroelectric capacitor.
But, as FRAMs become more highly integrated, it may be difficult to secure sufficient capacitance with a capacitor of a conventional flat-plate electrode. Thus, even the FRAM manufacturers are beginning to make bottom electrodes with cylindrical shapes in order to improve the ferroelectric surface area in a limited area of the more highly integrated devices.
FIGS. 1 through 3 are cross-sectional views to illustrate a problem of a conventional FRAM having a cylinder type capacitor.
Referring to FIGS. 1 through 3, the FRAM needs a contact plug 41 to connect the capacitor""s top electrode 36 with a capacitor plate line 50. But, in the event that the capacitor""s bottom electrode 32 is formed with the cylinder shape, the top electrode 36 may have a step difference. The step difference may become problematic when trying to form contact plug 41 connected to top electrode 36. That is, if the contact plug 41 is formed at a hollow position of the top electrode, as shown in FIG. 1, it may be difficult to form a contact hole given the required aspect ratio. Also, in the event a peripheral part 39 is formed and the contact plug 41 is connected to a high step of the capacitor top electrode 36, as shown in FIG. 2, there may be a problem as formation area changes. Further, the contact hole 43 may be formed with an incorrect alignment, as shown in FIG. 3, and the contact hole 43 may have to extend between the high step and the low step. Thus, it is difficult to form the contact hole 36 with a perfect depth for both the low step and the high step for the high step might be easily etch-damaged.
In accordance with exemplary embodiments, a FRAM comprises a top electrode that can be reliably connected to a capacitor plate line.
A FRAM in accordance with an exemplary embodiment of the present invention comprises a cylindrical type bottom electrode, a ferroelectric film thinly formed thereon, and a top electrode. A peripheral part of the ferroelectric film covers a cylindrical top of the capacitor""s bottom electrode. In an optional exemplary embodiment, the peripheral part is contiguous with that of a neighboring device, i.e. one continuous dielectric layer for multiple cells. The capacitor""s top electrode includes a first portion, a fill layer, and a second portion. The first portion of the top electrode includes a liner part; the top electrode may also include a peripheral part. The two portions contact the top surface of the ferroelectric film. The liner part for the top electrode is conformal to the ferroelectric, and will have substantially the same shape as a liner part of the ferroelectric film. A hallow define between the walls of the electrode""s liner part is filled with fill material to establish a fill layer. The fill material of the fill layer may be formed of polysilicon, silicon oxide or another material such as another metal. In one embodiment, the fill layer may comprise a fill material having a superior gap-fill capability or low stress relationship with respect to the material of the top electrode (which may comprise a metal or other conductive material). The top surface of the fill material of the fill layer and the peripheral part of the electrode are covered with the second portion to the top electrode.
The ferroelectric material may comprise one of PZT(Pb(Zr,Ti)O3) and SBT(SrBi2Ta2O9). These may be formed using chemical vapor deposition(CVD) technique instead of a coating technique that uses a sol gel change.
In a particular embodiment, the first and second portions of the top electrode may comprise the same material. For example, they may comprise a metal that is not easily oxidized at a high temperature or a metal that remains conductive in its oxidized state. Such metal may comprise platinum, ruthenium, iridium, rhodium, osmium or palladium.
In accordance with another exemplary embodiment, a method of forming a memory comprises forming an insulation layer over a substrate. The insulation layer is patterned to form a hole that exposes a region of the substrate. A bottom electrode material is formed conformal to the substrate and sidewalls that define the hole. A ferroelectric material is conformally formed over the bottom electrode. A first portion of a top electrode material layer is then formed conformal to and over the ferroelectric material. A hollow that is defined by where the first portion of the top electrode drops into the capacitor hole, such hollow is filled with fill material to establish a fill layer. A second portion of top electrode material is then formed over the material of the fill layer and a peripheral part of the first portion of the top electrode.
In one embodiment, after forming a layer of material for the bottom electrode, chemical-mechanical polishing (CMP) may be performed until exposing a region of the insulation layer outside the outline of the hole.
In a further embodiment, the fill layer is formed to a thickness sufficient to fill the hollow (i.e., within a cylindrical shape defined by walls to the first portion of the top electrode). The fill material or fill layer may then be planarization-etched, e.g., using anisotropic etching or chemical-mechanical polishing (CMP).
In another embodiment, a protection layer may be formed over the ferroelectric film and the fill material of the fill layer may comprise silicon oxide. In this embodiment, the protective layer may comprise a hydrogen barrier and can be formed to prevent the ferroelectric film from being affected by hydrogen that may be generated during the process of filling the hollow with the fill material to establish the fill layer. Subsequently portions of the protection layer might then be removed together with some of the fill material of the fill layer during its planarization-etching.
In order to prevent oxidation of a conductivity region of the substrate, in accordance with a further embodiment, an oxidation barrier layer is also to be formed over the substrate after the hole has been formed in the insulation layer, and before forming the bottom electrode.